n channel MOS

n channel MOS or NMOS is used in very large scale integrated (VLSI) circuits. nMOS can be fabricated by polysilicon gate self-aligning process. First step is cutting a thin wafer from a single crystal of silicon of high purity. Now p type impurity is introduced on to the wafer. Boron is the commonly used impurity and doping concentration is in the range 10¹⁵ to 10¹⁶ per cubic centimeter. The yielded wafer offer a resistivity ranging between 1-25 ohm-cm. Over this wafer, a layer of silicon dioxide is grown. This is for overall protection of the wafer. A photo resistive material also can be drawn over the wafer for more protection. The photo resistive material is exposed to UV radiation through a mask. The mask position decides the space for diffusion to take place. The masked regions are etched and heavily doped polysilicon is deposited by chemical vapour deposition method. Diffusion is achieved by heating the wafer in the presence of a gas in which phosphorous is contained. Again silicon dioxide and photo resistive material growing is carried out. For CMOS fabrication, entirely different mechanisms are employed. Some examples are p-well, n-well, twin-tub and silicon-on-insulator methods.